The present invention relates to a method of forming a scan path network and a semiconductor integrated circuit having a scan path network. Scan path networks are a technique for effectively carrying out testing of the operation of semiconductor integrated circuits. This technique is described, for example, in the following technical paper.
"A method of length minimization and short path error correction for scan path", Proceedings of the 52nd national convention of information processing society of Japan, No. 6, P27-28, 1996, Nakamura, Kobayashi, et al, "scan path line length optimization and hold time compensation techniques", P.27-28.
In order to increase the degree of integration of a circuit, it is preferable to make a scan path (the length of the path (wiring) from a scan-in pad to a scan-out pad) short. However, if the scan path is simply made short, there is the possibility that hold time errors will occur. Therefore, in the above technical paper, after connection (the connecting of each circuit using wiring) is complete, a step is executed where hold time error verification is carried out and buffers are then inserted at prescribed places (places where hold time errors occur) on the scan path.
However, with the kind of method in this technical paper, timing verification of each circuit has to be carried out again, thereby lengthening the design period of a semiconductor integrated circuit. A scan path network forming method that shortens the design period is therefore desired.